Author: Marcin Slusarz <marcin.slusarz@gmail.com> Commit 1bd751c1abc1029e8a0ae63ef4f19357c735a2a3 (« Staging: et131x: Clean up rxdma_csr ») changed csr from bitfield to u32, but failed to convert 2 uses of halt_status bit. It did: – if (csr.bits.halt_status != 1) + if ((csr & 0x00020000) != 1) which is wrong, because second version is always true. Fix it. This bug was found …